EE2020 Report on Pseudo-Random Number Generator

Pseudo-Random Number Generator

A pseudo-random number generator is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers.  It is central in applications such as simulations, electronic games, and cryptography. This report involves the design for building a basic pseudo-random number generator, and how the design is being carried out.  

Objectives

1. Implement a 4-bits pseudo-random number generator defined by xk+1= (axk+c) mod m. Set a = 2, c = output of a 4-bit counter and m = 5. x0 can be keyed in by a 4-bit DIP switch.
2. A push button resets back to the initial state, x0.
3. A 7-segment displays the current number only if it is less than the previous number. Otherwise, nothing will be displayed on the 7-segment.

Design Overview

The system can be separated into three main blocks. A 2xk+ccircuit is implemented to read in initial state value from DIP and perform the operation by using an adder and counter. The sum is pass to mod 5 circuit to get the remainder. The output then feedback to 2xk+ccircuit to read the next state value. The display circuit will hold the current value xk+1as well as the previous value xk. A magnitude comparator is used to compare these two values and display xk+1if it is less that  xk.

Figure 1: General design

Implementation

2Xk+C and reset control

74157 multiplexer is introduced to select between the read-in of the initial state or the subsequent states. The select signal is controlled by the push button. When the button is being pressed and hold, the next rising edge of the clock triggers select signal to be LOW for exactly one clock duration. The system is reset back to the initial state with multiplexer output the value from DIP switch. After which the select signal goes back to HIGH and remains HIGH. Multiplexer will then output the value obtained from mod 5 circuit.

Figure 2 shows the result of doubling a 4-bits number. It can be observed that by shifting the connections one bit to the left and wire the LSB to ‘0’, it is able to obtain 2xkwithout using any IC chip. The c value is obtained from a 74191 counter that counts up from 0000 to 1111. With its LD connected to the select signal, it will load back to 0000 when the system resets. The outputs from the multiplexer and the counter are feed into a 74283 adder.

xk	2xk
0001	0010
0010	0100
0011	0110
0100	1000

Figure 2: Doubling a 4-bits number

Figure 3: 2xk+ccircuit

Mod 5

The output from the 2xk+c circuit is input to an adder and adds 0110 (6). If the result does not generate a carry, it shows the input number is less than 10. If the input is greater or equals to 10, a carry will be generated and the 4-bit adder output will be input+6-16which is equivalent to input-10. This reduces the input to a magnitude that is less than 10. The outputs from 2xk+c circuit and adder go into a multiplexer with adder’s CARRY OUT as the select signal. When CARRY OUT is ‘0’, the original number is less than 10, thus select the output from 2xk+ccircuit. When CARRY OUT is ‘1’, the original number is greater or equals to 10, but after minus 10 it will be less than 10, thus select the adder output. After obtain a number that is less than 10, the process repeats again. However, instead of adding 6, the second adder adds 1011 (11). Carry will be generated if the input is greater or equals to 5. Thus, the second multiplexer will output the mod 5 result.

The result is input to a shift register to hold for one clock duration. While shift register’s output is holding the value, it is feedback to the 2xk+ccircuit to perform the next operation.

Figure 4: Mod 5 circuit

7-segment display

A 7-segment displays the current number xk+1only if it is less than the previous number xk. These two numbers can be obtained from the input and output of the shift register. The input stores the current value xk+1 while the output holds the previous value xk. A magnitude comparator is used to compare these two values and output a signal when xk+1is smaller than xk.

Signal from magnitude comparator will be HIGH only if xk+1< xk. This signal goes into the BI/RBO pin of the BCD-to-seven-segment decoder. If BI/RBO receives a LOW logic, all display will be blanked out. If it receives a HIGH logic, the decoder will decode the 4-bit input and display the corresponding decimal value on the common anode LED display.   

Figure 5: BCD-7-segment display

Experiment Results

Figure 6 shows the predicted results when DIP switch is set to 0001. The system is able to output the correct  (2xk+1+c) mod 5value. After blank-out current outputs that are larger or equal to the previous output, only values quoted with ‘display’ is displayed. Whenever the push button is pressed, the system resets back to its initial state at the next rising edge clock. Thus, the system is able to meet all the project requirements.

Figure 6: Predicted outputs

Repeated Counter Output

The counter will repeat 0000 twice after the system is reset back to the initial state by the push button. This is because the push button signal is aligned with the clock signal. When the push button signal goes LOW, it stays LOW for the entire clock duration, during this period counter inputs reflect to outputs which are 0000. When the push button signal goes back to HIGH after one clock duration, its rising edge overlaps with the rising edge of the clock. This prevents the counter from reacting to this clock rising edge, and it remains 0000 till the next clock rising edge.

If this repetition is not desired, the counter’s load signal can be modified such that it is able to react to the first clock rising edge after the system resets. Connect the push button as shown in Figure 7 below. The resultant output will be LOW when the button is being pressed, and HIGH when released. Input this new signal to the counter load pin while keeping the original push button signal connected to the multiplexer select pin. To reset, press and hold the pushbutton. The load signal goes LOW immediately, counter load back to 0000. The select signal goes LOW when there is a clock rising edge, multiplexer select the initial value. Release the push button while the select signal is still LOW, this will start the counting process from 0000. At the next clock rising edge, the multiplexer will select x1and counter will count up to 0001. A LED connected to the select signal may serve as an indicator for the timing to release the push button.

    

Figure 7: Load signal

Conclusion

This project provides a good exposure to various wiring skills. Most of the ICs used in this project involves 4-bit parallel inputs and outputs. This requires a very systematic way of color coding and the placement of ICs. Instead of using different color to represent different sub-blocks, it will be easier to observe if different color represents different 4-bit value at any point of time. Also, due to the limited space (two breadboards), it is extremely crucial to implement this project in an area efficient way. Thus, the experience gained from this project better equipped me for future journey.